Freescale Semiconductor PowerPC e500 Core - Chapter 8 Debug Support; Overview; Programming Model; Register Set

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 8-1
Chapter 8
Debug Support
This chapter discusses the debug features of the e500v1 and e500v2 core complex, with particular
attention given to the e500 debug facility as an implementation of the Book E–defined debug
architecture. Additional debug capabilities associated with an integrated device that implements
the e500 core are documented in the reference manual for that device.
References to e500 apply to both the e500v1 and the e500v2.
8.1 Overview
Internal debug mechanisms allow for software and hardware debug by providing debug functions,
such as instruction and data breakpoints and program trace mode. e500 debug facilities consist of
a set of software-accessible debug registers and interrupt mechanisms largely defined by the
Book E PowerPC architecture.
8.2 Programming Model
This section describes the registers, instructions, and interrupts defined by the Book E architecture
to support the debug facility.
8.2.1 Register Set
The Book E architecture defines the special-purpose registers (SPRs) listed in Table 8-1 for use
with the debug facilities. SPRs not implemented on the e500 are indicated. This table gives
cross-references to full descriptions of these SPRs in Chapter 2, “Register Model.”
Table 8-1. Debug SPRs
SPR Name
Defined SPR Number
Access
Supervisor
Only
Section/
Page
Decimal Binary
CSRR0 Critical save/restore register 0 58 00001 11010 R/W Yes 2.7.1.1/2-18
CSRR1 Critical save/restore register 1 59 00001 11011 R/W Yes 2.7.1.1/2-18
DAC1
1
Data address compare 1 316 01001 11100 R/W Yes 2.13.4/2-48
DAC2
1
Data address compare 2 317 01001 11101
DBCR0 Debug control register 0 308 01001 10100 R/W Yes 2.13.1/2-46
DBCR1 Debug control register 1 309 01001 10101 R/W Yes
DBCR2 Debug control register 2 310 01001 10110 R/W Yes