PowerPC e500 Core Family Reference Manual, Rev. 1
2-16 Freescale Semiconductor
Register Model
2.6.2 Timer Status Register (TSR)
The e500 implements the TSR as it is defined by the Book E architecture. The 32-bit TSR contains
status on timer events and the most recent watchdog timer-initiated processor reset. All TSR bits
function as write-1-to-clear.
2.6.3 Time Base (TBU and TBL)
The e500 implements the time base registers as they are defined by the Book E architecture. The
time base (TB) is composed of two 32-bit registers, the time base upper (TBU) concatenated on
the right with the time base lower (TBL). TB provides timing functions for the system. TB is a
volatile resource and must be initialized during start-up.
2.6.4 Decrementer Register (DEC)
The e500 implements the DEC as it is defined by the Book E architecture. DEC is a 32-bit
decrementing counter that is updated at the same rate as the TB. It provides a way to signal a
decrementer interrupt after a specified period unless one of the following occurs:
• DEC is altered by software in the interim.
• The TB update frequency changes.
DEC is typically used as a general-purpose software timer. The decrementer auto-reload register
is used to automatically reload a programmed value into DEC, as described in Section 2.6.5,
“Decrementer Auto-Reload Register (DECAR).”
2.6.5 Decrementer Auto-Reload Register (DECAR)
The e500 implements the DECAR as it is defined by the Book E architecture. If the auto-reload
function is enabled (TCR[ARE] = 1), the auto-reload value in DECAR is written to DEC when
DEC decrements from 0x0000_0001 to 0x0000_0000. Note that writing DEC with zeros by using
an mtspr[DEC] does not automatically generate a decrementer exception.
2.6.6 Alternate Time Base Registers (ATBL and ATBU)
The alternate time base counter (ATB), shown in Figure 2-7, is formed by concatenating the upper
and lower alternate time base registers (ATBU and ATBL). ATBL (SPR 526) provides read-only
43–46 WPEXT Watchdog timer period extension (see the description for WP)
47–50 FPEXT Fixed-interval timer period extension (see the description for FP)
Table 2-5. TCR Implementation-Specific Field Descriptions (continued)
Bits Name Description
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