Freescale Semiconductor PowerPC e500 Core - Reset; Little-Endian Mode

PowerPC e500 Core Family Reference Manual, Rev. 1
1-34 Freescale Semiconductor
Core Complex Overview
1.13.5 Reset
Book E–compliant cores do not share a common reset vector with the AIM version of the
PowerPC architecture. Instead, at reset fetching begins at address 0xFFFF_FFFC. In addition to
the Book E reset definition, the EIS and the e500 define specific aspects of the MMU page
translation and protection mechanisms. Unlike the AIM version of the PowerPC core, as soon as
instruction fetching begins, the e500 core is in virtual mode with a hardware-initialized TLB entry.
EIS–defined aspects of the MMU are described in the EREF. Specific details of how the e500 is
initialized are provided in Section 12.6, “TLB States after Reset.”
1.13.6 Little-Endian Mode
Unlike the AIM version of the PowerPC architecture, where little-endian mode is controlled on a
system basis, Book E allows control of byte ordering on a memory page basis. In addition, the
little-endian mode used in Book E is true little endian.