Freescale Semiconductor PowerPC e500 Core - Debug Control Registers (DBCR0-DBCR2); Debug Control Register 0 (DBCR0); Debug Control Register 1 (DBCR1)

PowerPC e500 Core Family Reference Manual, Rev. 1
2-46 Freescale Semiconductor
Register Model
2.13.1 Debug Control Registers (DBCR0–DBCR2)
The debug control registers are used to enable debug events, reset the processor, control timer
operation during debug events, and set the debug mode of the processor.
2.13.1.1 Debug Control Register 0 (DBCR0)
The e500 implements DBCR0 as it is defined by Book E (see the EREF for further details) with
the following exceptions:
• DBCR0[RST], bits 34–35, are implemented as shown in Table 2-31.
• IAC3 and IAC4 (DBCR0[42–43]) are not implemented.
Writing to DBCR0 requires synchronization, as described in Section 2.16, “Synchronization
Requirements for SPRs.”
2.13.1.2 Debug Control Register 1 (DBCR1)
The e500 implements DBCR1 as it is defined by the Book E architecture (see the EREF for more
information), except as follows:
• IAC1ER and IAC2ER values of 01 are reserved.
• IAC3US, IAC3ER, IAC4US, IAC4ER, and IAC34M (DBCR1[48–57]) are not
implemented.
Writing to DBCR1 requires synchronization, as described in Section 2.16, “Synchronization
Requirements for SPRs.” Table 2-32 describes the DBCR1 fields.
Table 2-31. DBCR0 Field Descriptions
Bits Name Description
34–35 RST Reset. Book E defines this field such that 00 is always no action and all other settings are implementation
specific. The e500 implements these bits as follows:
0
x Default (No action)
1
x Causes a hard reset if MSR[DE] and DBCR0[IDM] are set. Always cleared on subsequent cycle.
Table 2-32. DBCR1 Implementation-Specific Field Descriptions
Bits Name Description
34–35 IAC1ER Instruction address compare 1 effective/real mode
00 IAC1 debug events are based on effective addresses.
01 Reserved on the e500.
10 IAC1 debug events are based on effective addresses and can occur only if MSR[IS] = 0.
11 IAC1 debug events are based on effective addresses and can occur only if MSR[IS] = 1.
38–39 IAC2ER Instruction address compare 2 effective/real mode
00 IAC2 debug events are based on effective addresses.
01 Reserved on the e500.
10 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 0.
11 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 1.