Freescale Semiconductor PowerPC e500 Core - Book E Instructions with Implementation-Specific Features; E500 Instructions

Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-43
3.3.4 Book E Instructions with Implementation-Specific Features
Book E defines several instructions in a general way, leaving the details of the execution up to the
implementation. These are listed in Table 3-31. This section describes how the e500 core complex
implements those instructions. The implementation-specific TLB instructions (listed below) are
described in more detail in Section 12.4, “TLB Instructions—Implementation.”
A list of user-level instructions defined by both the classic PowerPC architecture and Book E can
be found in Section 3.10, “Instruction Listing.”
3.3.5 e500 Instructions
The e500 core complex implements the new instructions listed in Table 3-32 (with cross
references to more detailed descriptions) that extend the Book E instruction set in accordance with
Book E. SPE and embedded floating-point APU instructions are listed in Table 3-36 and
Table 3-37.
Table 3-31. Implementation-Specific Instructions Summary
Name Mnemonic Syntax Category
TLB Invalidate Virtual Address Indexed tlbivax rA, rB These are described generally in Section 3.3.2.2.2,
“Supervisor-Level TLB Management Instructions.” They are
described in greater detail in Section 12.4, “TLB
Instructions—Implementation.”
TLB Read Entry tlbre —
TLB Search Indexed tlbsx rA, rB
TLB Write Entry tlbwe —
Table 3-32. e500-Specific Instructions (Except SPE and SPFP Instructions)
Name Mnemonic Syntax Section #/Page
Branch Buffer Load Entry and Lock Set bblels — 3.9.1/3-63
Branch Buffer Entry Lock Reset bbelr —
Data Cache Block Lock Clear dcblc CT, rA, rB 3.8.4/3-61
Data Cache Block Touch and Lock Set dcbtls CT, rA, rB
Data Cache Block Touch for Store and Lock Set dcbtstls CT, rA, rB
Instruction Cache Block Lock Clear icblc CT, rA, rB
Instruction Cache Block Touch and Lock Set icbtls CT, rA, rB
Integer Select isel rD, rA, rB, crB 3.8.2/3-60
Move from Performance Monitor Register mfpmr rD,PMRN 3.8.2/3-60
Move to Performance Monitor Register mtpmr PMRN,rS
Return from Machine Check Interrupt rfmci — 3.8.5/3-63