Freescale Semiconductor PowerPC e500 Core - Recommended Simplified Mnemonics

PowerPC e500 Core Family Reference Manual, Rev. 1
3-42 Freescale Semiconductor
Instruction Model
Implementation Note—The presence and exact semantics of the TLB management instructions
are implementation dependent. To minimize compatibility problems, system software should
incorporate uses of these instructions into subroutines.
3.3.3 Recommended Simplified Mnemonics
The description of each instruction includes the mnemonic and a formatted list of operands.
Book E–compliant assemblers support the mnemonics and operand listed. To simplify assembly
language programming, a set of simplified mnemonics and symbols is provided for some of the
most frequently used instructions; refer to Appendix C, “Simplified Mnemonics for PowerPC
Instructions,” for a complete list. Programs written to be portable across the various assemblers
for the Book E architecture should not assume the existence of mnemonics not described in this
document.
TLB Search
Indexed
tlbsx rA, rB tlbsx updates the MAS registers conditionally based on the success or failure of a lookup
in the MMU. The lookup is controlled by the EA provided by GPR[rB] specified in the
instruction encoding and MAS6[SAS,SPID]. The values placed into MAS registers differ,
depending on whether a successful or unsuccessful search occurred. See Section 12.3,
“Translation Lookaside Buffers (TLBs).”
The RTL for the e500 implementation of tlbsx is as follows:
if RA!=0 then generate exception
EA =
32
0 || GPR(RB)
32:63
ProcessID = MAS6(SPID), 0b0000_0000
AS = MAS6(SAS)
VA = AS || ProcessID || EA
if Valid_TLB_matching_entry_exists (VA)
then result = see Table 12-15, column “tlbsx hit”
else result = see Table 12-15, column “tlbsx miss”
MAS0, MAS1, MAS2, MAS3, and MAS7 = result
Note that RA=0 is a preferred form for tlbsx and that some Freescale implementations,
such as the e500, take an illegal instruction exception program interrupt if RA != 0.
TLB
Synchronize
tlbsync — Causes a TLBSYNC transaction on the e500 core complex bus. This transaction is retried
if any processor, including the one that executed the tlbsync, has pending memory
accesses issued before any previous tlbivax completed.See Section 12.3, “Translation
Lookaside Buffers (TLBs).”
The e500 broadcasts cache tlbsync only if ABE = 1 to allow management of external L2
caches (for implementations with L2 caches) as well as other L1 caches in the system
TLB Write
Entry
tlbwe — tlbwe causes the contents of certain fields of MAS0, MAS1, MAS2, and MAS3 (and MAS7
on e500v2) to be written into a single TLB entry in the MMU. The entry written is specified
by the TLBSEL, ESEL, and EPN fields of MAS0 and MAS2. Execution of tlbwe on the
e500v2 core also causes the upper 4 bits of the RPN that reside in MAS7 to be written to
the selected TLB entry. See Section 12.3, “Translation Lookaside Buffers (TLBs).”
The RTL for the e500 implementation of tlbwe is as follows:
tlb_entry_id = MAS0(TLBSEL, ESEL)|| MAS2(EPN)
MMU(tlb_entry_id) = MAS0, MAS1, MAS2, MAS3, (and MAS7 on e500v2)
Table 3-30. TLB Management Instructions (continued)
Name Mnemonic Syntax Implementation Notes