Register Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 2-45
The MAS6 fields are described in Table 2-29.
2.12.5.7 MAS Register 7 (MAS7)—e500v2 Only
The MAS7 register contains the high-order address bits of the RPN for implementations that
support more than 32 bits of physical address. (The e500v1 supports 32-bit addresses, while the
e500v2 supports 36-bit real addresses.) Implementations that do not support more than 32 bits of
physical addressing do not implement MAS7. Figure 2-35 shows the format of the MAS7 register.
Writing to MAS0 requires synchronization, as described in Section 2.16, “Synchronization
Requirements for SPRs
The MAS7 fields are described in Table 2-30.
2.13 Debug Registers
This section describes debug-related registers that are accessible to software running on the
processor. These registers are intended for use by special debug tools and debug software, and not
by general application or operating system code.
Table 2-29. MAS6 Field Descriptions
Bits Name Description
32–39 — Reserved, should be cleared.
40–47 SPID0 Search PID0. Specifies the value of PID0 used when searching the TLB during execution of tlbsx. For the e500
implementation, this field contains the 8-bit search PID0 value. Specifies the value of PID0 used when searching
the TLB during execution of tlbsx.
48–62 — Reserved, should be cleared.
63 SAS Address space (AS) value for searches. Specifies the value of AS used when searching the TLB during
execution of tlbsx.
SPR 944 Access: Supervisor-only
32 59 60 63
R
—RPN
W
Reset All zeros
Figure 2-35. MAS Register 7 (MAS7)
Table 2-30. MAS7 Field Descriptions—High-Order RPN
Bits Name Description
32–59 — Reserved, should be cleared.
32–63 RPN Real page number, 4 high-order bits. MAS3 holds the remainder of the RPN. The byte offset
within the page is provided by the EA and is not present in MAS3 or MAS7.
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