Freescale Semiconductor PowerPC e500 Core - MAS Register Updates

PowerPC e500 Core Family Reference Manual, Rev. 1
12-32 Freescale Semiconductor
Memory Management Units
12.7.2 MAS Register Updates
Table 12-15 summarizes the updates to each MAS register field for each update stimulus.
Table 12-15. MMU Assist Register Field Updates
MAS Register
Bit/Field
Value Loaded for Each Case
Instr/Data TLB Error tlbsx Hit tlbsx Miss ISI DSI tlbre tlbwe
TLBSEL TLBSELD Which TLB hit TLBSELD — — — —
ESEL if TLBSELD = 0:
TLB0[NV]
else, undefined
Number of entry
that hit
if TLBSELD = 0:
TLB0[NV]
else, undefined
—— — —
NV if TLBSELD = 0:
~TLB0[NV]
else, undefined
if TLBSEL = 0:
TLB0[NV]
else, undefined
if TLBSELD = 0:
~TLB0[NV]
else, undefined
— — if TLBSEL = 0:
TLB0[NV]
else, undefined
—
V110——V(array)—
IPROT 0 Matched IPROT
if TLB1 hit;
else 0
0 — — IPROT (array)
if TLB1; else 0
—
TID[0–7] Value of PID register
selected by TIDSELD
TID (array) SPID0 — — TID (array) —
TS MSR[IS/DS] SAS SAS — — TS(array) —
TSIZE[0–3] TSIZED TSIZE(array) TSIZED — — TSIZE(array) —
EPN[32–51] EPN of access EPN (array) — — — EPN (array) —
X0, X1
WIMGE
X0D, X1D
WIMGED
X0, X1 (array)
WIMGE (array)
X0D, X1D
WIMGED
— — X0, X1 (array)
WIMGE (array)
—
RPN[28–51] Zeros RPN (array) Zeros — — RPN (array) —
Access
(PERMIS + U0–U3)
Zeros Access (array) Zeros — — Access (array) —
TLBSELD — — — — — — —
TIDSELD[0–1] — — — — — — —
TSIZED[0–3] — — — — — — —
WIMGED — — — — — — —
SPID0 PID0 — — — — — —
SAS MSR[IS] for
instruction access;
MSR[DS] for data
access
——————