PowerPC e500 Core Family Reference Manual, Rev. 1
2-22 Freescale Semiconductor
Register Model
2.7.2 e500-Specific Interrupt Registers
This section describes machine check save/store and syndrome registers.
2.7.2.1 Machine Check Save/Restore Register 0 (MCSRR0)
When a machine check interrupt is taken, MCSRR0, shown in Figure 2-11, is set to the address of
the instruction where the interrupted process should resume. The instruction is interrupt-specific,
although typically MCSRR0 holds the address of the instruction that caused the interrupt. After
rfmci executes, instruction execution continues at this address.
2.7.2.2 Machine Check Save/Restore Register 1 (MCSRR1)
MCSRR1 is used to save and restore machine state on machine check interrupts. When a machine
check interrupt is taken, MSR contents are placed into MCSRR1, shown in Figure 2-12. When
rfmci executes, MCSRR1 contents are restored to MSR. MCSRR1 bits that correspond to
reserved MSR bits are also reserved; reserved MSR bits may be altered.
2.7.2.3 Machine Check Address Register (MCAR)
When the core complex takes a machine check interrupt, it updates MCAR (Figure 2-13) to
indicate the address of the data associated with the machine check. Note that if a machine check
interrupt is caused by a signal, the contents of MCAR are not meaningful.
SPR 570 Access: Supervisor-only
32 63
R
Next instruction address
W
Reset All zeros
Figure 2-11. Machine Check Save/Restore Register 0 (MCSRR0)
SPR 571 Access: Supervisor-only
32 63
R
MSR state information
W
Reset All zeros
Figure 2-12. Machine Check Save/Restore Register 1 (MCSRR1)
SPR 573 Access: Supervisor-only
32 63
R
Machine check address
W
Reset All zeros
Figure 2-13. Machine Check Address Register (MCAR)
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