Freescale Semiconductor PowerPC e500 Core - L1 MMU TLB Organization

PowerPC e500 Core Family Reference Manual, Rev. 1
12-10 Freescale Semiconductor
Memory Management Units
Figure 12-5 shows the organization of the L1 TLBs in both the instruction and data L1 MMUs.
Figure 12-5. L1 MMU TLB Organization
L1TLB4K TLB entries are replaced based on a true LRU algorithm. The L1VSP entries are also
replaced based on a true LRU replacement algorithm. The LRU bits are updated each time a TLB
entry is accessed for translation. However, there are other speculative accesses performed to the
L1 MMUs that cause the LRU bits to be updated. The performance of the L1 MMUs is high, even
though it is not possible to predict (externally) exactly which entry is the next to be replaced.
V
V
0
3
L1VSP
V
0
15
Select
Compare
Compare
MUX
RPN
hit
V
Compare
Compare
Compare
Compare
Compare
Compare
RPN
hit
L1TLB4K
Real Address
(translated bits,
depending on page size)
Virtual Addresses
1
2
VAs