Freescale Semiconductor PowerPC e500 Core - Data Address Compare Debug Event; Data Address Compare Read;Write Enable

Debug Support
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 8-9
If MSR[DE] is cleared at the time of the instruction address compare debug exception, a debug
interrupt does not occur and the instruction completes execution (provided the instruction is not
causing another exception that generates an enabled interrupt).
Later, if the debug exception has not been reset by clearing the appropriate DBSR[IACn], bits and
MSR[DE] is set, a delayed debug interrupt occurs. In this case, CSRR0 contains the address of the
instruction following the one that set DE. Software in the debug interrupt handler can observe
DBSR[IDE] to determine how to interpret the CSRR0 value.
8.4.2 Data Address Compare Debug Event
One or more data address compare debug events (DAC1R, DAC1W, DAC2R, or DAC2W) can
occur if they are enabled, execution of a data access instruction is attempted, and the type, address,
and possibly even the data value of the data access meet the criteria specified in DBCR0, DBCR2,
DAC1, and DAC2.
8.4.2.1 Data Address Compare Read/Write Enable
DBCR0[DAC1] specifies whether DAC1R debug events can occur on read-type data accesses and
whether DAC1W debug events can occur on write-type data accesses.
DBCR0[DAC2] specifies whether DAC2R debug events can occur on read-type data accesses and
whether DAC2W debug events can occur on write-type data accesses.
All load instructions are considered reads with respect to debug events, and all store instructions
are considered writes with respect to debug events. In addition, cache management instructions,
and certain special cases, are handled as follows.
• dcbt, dcbtst, icbt, and icbi are all considered reads with respect to debug events. Note that
dcbt, dcbtst, and icbt are treated as no-ops when they report data storage or data TLB miss
exceptions, instead of being allowed to cause interrupts. However, these instructions are
allowed to cause debug interrupts, even when no-op would have been asserted due to a data
storage or data TLB miss exception.
• dcbz, dcbi, dcbf, and dcbst are all considered writes with respect to debug events. Note
that dcbf and dcbst are considered reads with respect to data storage exceptions because
they do not change the data at a given address. However, because execution of these
instructions may generate write activity on the processor’s data bus, they are treated as
writes with respect to debug events.