PowerPC e500 Core Family Reference Manual, Rev. 1
5-30 Freescale Semiconductor
Interrupts and Exceptions
5.7.14 Debug Interrupt
A debug interrupt occurs when no higher priority interrupt exists, a debug exception exists in the
DBSR, and debug interrupts are enabled (DBCR0[IDM] = 1 and MSR[DE] = 1). A debug
exception occurs when a debug event causes a corresponding DBSR bit to be set. The “Debug
Support” chapter of the EREF describes Book E and EIS aspects of the debug interrupt.
Note that on the e500, if DBCR0[IDM] is cleared, no debug events occur. That is, irrespective of
MSR, DBCR0, DBCR1, and DBCR2 settings, no debug events are logged in DBSR and no debug
interrupts are taken. If DBCR0[IDM] is set, Book E debug mode functions as specified in Book E
(according to the value of MSR[DE] and the values of DBCR0, DBCR1, and DBCR2).
The e500 core complex complies with the Book E debug definition, except as follows:
• Data address compare is only supported for effective addresses.
• Instruction address compares IAC3 and IAC4 are not supported.
• Instruction address compare is only supported for effective addresses.
• DVC is not supported.
CSRR0, CSRR1, MSR, and DBSR are updated as shown in Table 5-28.
Instruction execution resumes at address IVPR[32–47] || IVOR15[48–59] || 0b0000.
Table 5-28. Debug Interrupt Register Settings
Register Setting
CSRR0 For debug exceptions that occur while debug interrupts are enabled (DBCR0[IDM] = 1 and MSR[DE] = 1),
CSRR0 is set as follows:
• For instruction address compare (IAC registers), data address compare (DAC1R, DAC1W, DAC2R, and
DAC2W), trap (TRAP), or branch taken (BRT) debug exceptions, set to the address of the instruction
causing the debug interrupt.
• For instruction complete (ICMP) debug exceptions, set to the address of the instruction that would have
executed after the one that caused the debug interrupt.
• For unconditional debug event (UDE) debug exceptions, set to the address of the instruction that would
have executed next if the debug interrupt had not occurred.
• For interrupt taken (IRPT) debug exceptions, set to the interrupt vector value of the interrupt that caused
the interrupt taken debug event.
• For return from interrupt (RET) debug exceptions, set to the address of the instruction that would have
executed after the rfi, rfci, or rfmci that caused the debug interrupt.
• For debug exceptions that occur while debug interrupts are disabled (DBCR0[IDM] = 0 or MSR[DE] = 0),
a debug interrupt occurs at the next synchronizing event if DBCR0[IDM] and MSR[DE] are modified such
that they are both set and if the debug exception status is still set in the DBSR. When this occurs, CSRR0
holds the address of the instruction that would have executed next, not the address of the instruction that
modified DBCR0 or MSR and thus caused the interrupt.
CSRR1 Set to the MSR contents at the time of the interrupt.
MSR ME is unchanged. All other MSR bits are cleared.
DBSR Set to indicate type of debug event. (See Section 2.13.2, “Debug Status Register (DBSR).”)
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