Freescale Semiconductor PowerPC e500 Core - MAS Register 6 (MAS6)

PowerPC e500 Core Family Reference Manual, Rev. 1
2-44 Freescale Semiconductor
Register Model
The MAS4 fields are described in Table 2-28.
2.12.5.6 MAS Register 6 (MAS6)
Figure 2-34 shows the format of MAS6. Note that while the Freescale Book E allows for an SPIDx
field of 12 bits, SPID0 on the core complex is only an 8-bit field. Writing to MAS6 requires
synchronization, as described in Section 2.16, “Synchronization Requirements for SPRs.”
Table 2-28. MAS4 Field Descriptions—Hardware Replacement Assist Configuration
Bits Name Description
32–33 — Reserved, should be cleared.
34–35 TLBSELD TLBSEL default value. 2-bit field that specifies the default value to be loaded in MAS0[TLBSEL] on
a TLB miss exception.
36–45 — Reserved, should be cleared.
46–47 TIDSELD TID default selection value. Defined by the EIS as a 4-bit field that specifies which of the current PID
registers should be used to load the MAS1[TID] field on a TLB miss exception.
The e500 implementation defines bits 44–45 as reserved and bits 46–47 as follows:
00 PID0
01 PID1
10 PID2
11 TIDZ (0x00) (all zeros)
48–51 — Reserved, should be cleared.
52–55 TSIZED Default TSIZE value. Specifies the default value to be loaded into MAS1[TSIZE] on a TLB miss
exception.
56 — Reserved, should be cleared.
57 X0D Default X0 value. Specifies the default value to be loaded into MAS2[X0] on a TLB miss exception.
58 X1D Default X1 value. Specifies the default value to be loaded into MAS2[X1] on a TLB miss exception.
59 WD Default W value. Specifies the default value to be loaded into MAS2[W] on a TLB miss exception.
60 ID Default I value. Specifies the default value to be loaded into MAS2[I] on a TLB miss exception.
61 MD Default M value. Specifies the default value to be loaded into MAS2[M] on a TLB miss exception.
62 GD Default G value. Specifies the default value to be loaded into MAS2[G] on a TLB miss exception.
63 ED Default E value. Specifies the default value to be loaded into MAS2[E] on a TLB miss exception.
SPR 630 Access: Supervisor-only
32 39 40 47 48 62 63
R
—
SPID0 — SAS
W
Reset All zeros
Figure 2-34. MAS Register 6 (MAS6)