Freescale Semiconductor PowerPC e500 Core - General Instruction Flow

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-11
Branch prediction is performed in parallel with the fetch stages using the branch prediction unit
(BPU), which incorporates the branch target buffer (BTB). Predictions are resolved in the branch
unit (BU). Incorrect predictions are handled as follows:
1. Fetch is redirected to the correct path, and mispredicted instructions are purged.
2. The mispredicted branch is marked as such in the CQ.
3. Eventually, the branch is retired and the CQ, issue queue, and execution units are flushed.
If the correct-path instructions reach the IQ before the back half of the pipeline is flushed,
they stall in the IQ until the flush occurs.
After an instruction executes, results are made available to subsequent instructions in the
appropriate rename registers. The architecture-defined GPRs are updated in the write-back stage.
Branch instructions that update LR or CTR write back in a similar fashion.
If a later instruction needs the result as a source operand, the result is simultaneously made
available to the appropriate execution unit, which allows a data-dependent instruction to be
decoded and dispatched without waiting to read the data from the architected register file. Results
are then stored into the correct architected GPR during the write-back stage. Branch instructions
that update either the LR or CTR write back their results in a similar fashion.
Section 4.3.1, “General Instruction Flow,” describes this process.
4.3.1 General Instruction Flow
To resolve branch instructions and improve the accuracy of branch predictions, the e500
implements a dynamic branch prediction mechanism using the 512-entry BTB, a four-way set
associative cache of branch target effective addresses. A BTB entry is allocated whenever a branch
resolves as taken—unallocated branches are always predicted as not taken. Each BTB entry holds
a 2-bit saturating branch history counter whose value is incremented or decremented depending
on whether the branch was taken. These bits can take four values: strongly taken, weakly taken,
weakly not taken, and strongly not taken. This mechanism is described in Section 4.4.1.2, “BTB
Branch Prediction and Resolution.”
The e500 does not implement the static branch prediction that is defined by the PowerPC
architecture. The BO[y] prediction in branch encodings is ignored.
Dynamic branch prediction is enabled by setting BUCSR[BPEN]. Clearing BUCSR[BPEN]
disables dynamic branch prediction, in which case the e500 predicts every branch as not taken.
Branch instructions are treated like any other instruction and are assigned CQ entries to ensure that
the CTR and LR are updated sequentially.
The dispatch rate is affected by the serializing behavior of some instructions and the availability
of issue queues and CQ entries. Instructions are dispatched in program order; an instruction in IQ1
cannot be dispatched ahead of one in IQ0.