Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-27
Figure 12-12 describes the format of MAS1 on the e500 core complex. Note that while Freescale
Book E allows for a TID field of 12 bits, the TID field on the core complex is implemented as only
8 bits.
Table 12-9 shows the core complex MAS1 bit definitions.
44–47 ESEL Entry select. Number of the entry in the selected array to be used for tlbwe. This field is also updated on TLB
error exceptions (misses), and tlbsx hit and miss cases as shown in Table 12-15.
For the e500, ESEL serves as the way select for the corresponding TLB as follows:
When TLBSEL = 00 (TLB0 selected), bits 46–47 are used (and bits 44–45 should be cleared). This field
selects between way 0, 1, 2, or 3 of TLB0. EA bits 45–51 from MAS2[EPN] are used to index into the TLB to
further select the entry for the operation. Note that for the e500v1, bit 47 selects either way 0 or way 1, and
bit 46 should remain cleared.
When TLBSEL = 01 (TLB1 selected), all four bits are used to select one of 16 entries in the array.
48–61 — Reserved, should be cleared.
62–63 NV Next victim. Next victim value to be written to TLB0[NV] on execution of tlbwe. This field is also updated on
TLB error exceptions (misses), tlbsx hit and miss cases as shown in Table 12-15, and on execution of tlbre.
This field is updated based on the calculated next victim value for TLB0 (based on the round-robin
replacement algorithm, described in Section 12.3.2.2, “Replacement Algorithms for L2 MMU”). Note that for
the e500v1, bit 62 should remain cleared and only bit 63 has significance.
Note that this field is not defined for operations that specify TLB1 (when TLBSEL = 01).
SPR 625 Access: Supervisor-only
32 33 34 39 40 47 48 50 51 52 55 56 63
R
V IPROT — TID —TSTSIZE —
W
Reset All zeros
Figure 12-12. MAS Register 1 (MAS1)
Table 12-9. MAS1 Field Descriptions—Descriptor Context and Configuration
Control
Bits Name Descriptions
32 V TLB valid bit
0 This TLB entry is invalid.
1 This TLB entry is valid.
33 IPROT Invalidate protect. Set to protect this TLB entry from invalidate operations due to the execution of tlbiva[x] (TLB1
only). Note that not all TLB arrays are necessarily protected from invalidation with IPROT. Arrays that support
invalidate protection are denoted as such in the TLB configuration registers.
0 Entry is not protected from invalidation.
1 Entry is protected from invalidation. See Section 12.3.2.1, “IPROT Invalidation Protection in TLB1.”
34–39 — Reserved, should be cleared.
40–47 TID Translation identity. An 8-bit field that defines the process ID for this TLB entry. TID is compared with the current
process IDs of the three virtual address to be translated. A TID value of 0 defines an entry as global and
matches with all process IDs.
Table 12-8. MAS0 Field Descriptions—MMU Read/Write and Replacement Control
Bits Name Descriptions
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