Freescale Semiconductor PowerPC e500 Core - Recoverability from Interrupts

PowerPC e500 Core Family Reference Manual, Rev. 1
5-4 Freescale Semiconductor
Interrupts and Exceptions
— ESR[SPE], the SPE exception bit, is set when the processor reports an exception related
to the execution of SPFP or SPE instructions.
NOTE
The SPE APU and embedded floating-point APU functionality is
implemented in all PowerQUICC III devices. However, these
instructions will not be supported in devices subsequent to
PowerQUICC III. Freescale Semiconductor strongly recommends
that use of these instructions be confined to libraries and device
drivers. Customer software that uses SPE or embedded floating-point
APU instructions at the assembly level or that uses SPE intrinsics will
require rewriting for upward compatibility with next-generation
PowerQUICC devices.
Freescale Semiconductor offers a libmoto_e500 library that uses SPE
instructions. Freescale will also provide libraries to support
next-generation PowerQUICC devices.
• The debug exception implementation does not support IAC3, IAC4, DAC3, and DAC4
comparisons.
• The core complex supports instruction address compare (IAC1 and IAC2) and data address
compare (DAC1 and DAC2) for effective addresses only. Real-address support is not
provided.
• The e500 does not support the Book E–defined floating-point unavailable and auxiliary
processor unavailable interrupts.
• Data value compare (DVC) debug exceptions are not supported.
• The interrupt priorities differ from those specified in Book E as described in Section 5.11.1,
“e500 Exception Priorities.”
• Alignment exceptions. Vector operations can cause alignment exceptions as described in
Section 5.7.6, “Alignment Interrupt.”
• Book E and the machine check APU define sources of externally generated interrupts.
5.2.1 Recoverability from Interrupts
All interrupts except some machine check interrupts are recoverable. The state of the core complex
(return address and MSR contents) is saved when a machine check interrupt is taken. The
conditions that cause a machine check may or may not prohibit recovery. Section 5.7.2.1, “Core
Complex Bus (CCB) and L1 Cache Machine Check Errors,” provides additional information
about machine check recoverability.