Freescale Semiconductor PowerPC e500 Core - Paragraph Page; Number Title Number

PowerPC e500 Core Family Reference Manual, Rev. 1
vi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
1.9.3 Process ID Registers (PID0–PID2)............................................................................ 1-28
1.9.4 TLB Coherency.......................................................................................................... 1-28
1.10 Memory Coherency ....................................................................................................... 1-29
1.10.1 Atomic Update Memory References ......................................................................... 1-29
1.10.2 Memory Access Ordering.......................................................................................... 1-29
1.10.3 Cache Control Instructions ........................................................................................ 1-29
1.10.4 Programmable Page Characteristics .......................................................................... 1-30
1.11 Core Complex Bus (CCB) ............................................................................................. 1-30
1.12 Performance Monitoring................................................................................................ 1-30
1.12.1 Global Control Register............................................................................................. 1-31
1.12.2 Performance Monitor Counter Registers................................................................... 1-31
1.12.3 Local Control Registers ............................................................................................. 1-31
1.13 Legacy Support of PowerPC Architecture..................................................................... 1-32
1.13.1 Instruction Set Compatibility..................................................................................... 1-32
1.13.1.1 User Instruction Set ............................................................................................... 1-32
1.13.1.2 Supervisor Instruction Set...................................................................................... 1-32
1.13.2 Memory Subsystem ................................................................................................... 1-33
1.13.3 Exception Handling ................................................................................................... 1-33
1.13.4 Memory Management................................................................................................ 1-33
1.13.5 Reset........................................................................................................................... 1-34
1.13.6 Little-Endian Mode.................................................................................................... 1-34
Chapter 2
Register Model
2.1 Overview.......................................................................................................................... 2-1
2.2 e500 Register Model........................................................................................................ 2-2
2.2.1 Special-Purpose Registers (SPRs) ............................................................................... 2-5
2.3 Registers for Integer Operations...................................................................................... 2-9
2.3.1 General-Purpose Registers (GPRs).............................................................................. 2-9
2.3.2 Integer Exception Register (XER)............................................................................... 2-9
2.4 Registers for Branch Operations...................................................................................... 2-9
2.4.1 Condition Register (CR).............................................................................................. 2-9
2.4.2 Link Register (LR)..................................................................................................... 2-10
2.4.3 Count Register (CTR)................................................................................................ 2-10
2.5 Processor Control Registers........................................................................................... 2-10
2.5.1 Machine State Register (MSR).................................................................................. 2-10
2.5.2 Processor ID Register (PIR) ...................................................................................... 2-12
2.5.3 Processor Version Register (PVR)............................................................................. 2-13
2.5.4 System Version Register (SVR)................................................................................. 2-13