Freescale Semiconductor PowerPC e500 Core - Deviations from the Book E Debug Model

Debug Support
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 8-3
A debug interrupt occurs when no higher priority interrupt exists, a debug exception is indicated
in the DBSR, and debug interrupts are enabled (DBCR0[IDM] = MSR[DE] = 1). CSRR0, CSRR1,
MSR, and DBSR are updated as shown in Table 8-2.
Instruction execution resumes at address IVPR[32–47] || IVOR15[48–59] || 0b0000.
8.2.4 Deviations from the Book E Debug Model
The e500 core complex supports Book E debug mode with the following exceptions:
• Instruction address compare registers 3 and 4 (IAC3, IAC4) and data address compare
registers 3 and 4 (DAC3, DAC4) along with their debug exceptions, are not implemented.
• Only effective addresses are compared with instruction address compare (IAC1 or IAC2
debug events), and data address compare (DAC1 or DAC2 debug events).
• Return debug events for the rfci instruction are not logged if MSR[DE] is cleared (debug
interrupts are disabled).
Table 8-2. Debug Interrupt Register Settings
Register Setting
CSRR0 For debug exceptions that occur while debug interrupts are enabled (DBCR0[IDM] = 1 and MSR[DE] = 1), CSRR0 is
set as follows:
• For instruction address compare (IAC1 and IAC2 debug events), data address compare (DAC1R, DAC1W, DAC2R,
and DAC2W debug events), trap, or branch taken debug exceptions, set to the address of the instruction causing
the debug interrupt.
• For instruction complete debug exceptions, set to the address of the instruction that would have executed after the
one that caused the debug interrupt.
• For unconditional debug event (UDE) debug exceptions, set to the address of the instruction that would have
executed next if the debug interrupt had not occurred.
• For interrupt taken debug exceptions, set to the interrupt vector value of the interrupt that caused the interrupt taken
debug event.
• For return from interrupt (RET) debug exceptions, set to the address of the instruction that would have executed
after the rfi or rfci that caused the debug interrupt.
• For debug exceptions that occur while debug interrupts are disabled (DBCR0[IDM] = 0 or MSR[DE] = 0), a debug
interrupt occurs at the next synchronizing event if DBCR0[IDM] and MSR[DE] are modified such that they are both
set and if the debug exception status is still set in the DBSR. When this occurs, CSRR0 holds the address of the
instruction that would have executed next, not with the address of the instruction that modified DBCR0 or MSR and
thus caused the interrupt.
CSRR1 Set to the contents of the MSR at the time of the interrupt.
MSR ME is unchanged. All other MSR bits are cleared.
DBSR Set to indicate type of debug event (see Chapter 8, “Debug Support”).