Freescale Semiconductor PowerPC e500 Core - Replacement Algorithms for L2 MMU

Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-13
Only TLB entries in TLB1 can be protected from invalidation; entries in TLB0 and in the level 1
MMUs cannot be protected from invalidation (they don’t implement the IPROT bit). See the
EREF for more background information on the IPROT attribute.
Invalidation operations are guaranteed to invalidate the entry that translates the address specified
in the operand of the tlbivax instruction. Other entries may also be invalidated by this operation
if they are not protected with IPROT. A precise invalidation can be performed by writing a 0 to
the valid bit of a TLB entry. Note that successful invalidation operations in the L2 MMU also
invalidate matching entries in the L1 MMU.
If HID1[ABE] = 1, enabling broadcast operations on the core complex bus (CCB), execution of
tlbivax is broadcast onto the CCB, regardless of whether or not the invalidation was successful.
Flash invalidations (initiated by writing to the appropriate bits in MMUCSR0) are never broadcast.
12.3.2.2 Replacement Algorithms for L2 MMU
The replacement algorithm for TLB1 (the fully associative TLB in the L2 MMU) must be
implemented completely by the system software. Thus, when an entry in TLB1 is to be replaced,
the software selects which entry to replace and writes the entry number to the MAS0[ESEL] field
before executing a tlbwe instruction.
TLB0 entry replacement is also implemented by software. To assist the software with TLB0
replacement, the e500 core complex provides a hint that can be used for implementing a
round-robin replacement algorithm. The only parameter required to select the entry to replace is
the way select value for the new entry. (The entry within the way is selected by EA[45–51].) The
mechanism for the round-robin replacement uses the following bits:
• TLB0[NV]—the next victim field within TLB0
• MAS0[NV]—the next victim field of MAS0
• MAS0[ESEL]—selects the way to be replaced on tlbwe
See Table 12-15 for a complete description of MAS register updates on various exception
conditions.
Note that the system software can load any value into MAS0[ESEL] and MAS0[NV] prior to
execution of tlbwe, effectively overwriting this round robin replacement algorithm. In this case,
the value written by software into MAS0[NV] is used as the next TLB0[NV] value on a TLB miss.
Also, note that the value of MAS0[NV] is indeterminate after any TLB entry invalidate operation
(including a flash invalidate). If the software must know its value after an invalidate operation,
MAS0[NV] must be explicitly read.