Freescale Semiconductor PowerPC e500 Core - Interrupt Registers Defined by Book E; Save;Restore Register 0;1 (SRR0 and SRR1); Critical Save;Restore Register 0;1 (CSRR0 and CSRR1); Data Exception Address Register (DEAR)

PowerPC e500 Core Family Reference Manual, Rev. 1
2-18 Freescale Semiconductor
Register Model
2.7.1 Interrupt Registers Defined by Book E
This section describes the following register bits and their fields:
• Section 2.7.1.1, “Save/Restore Register 0/1 (SRR0 and SRR1)”
• Section 2.7.1.2, “Critical Save/Restore Register 0/1 (CSRR0 and CSRR1)”
• Section 2.7.1.3, “Data Exception Address Register (DEAR)”
• Section 2.7.1.4, “Interrupt Vector Prefix Register (IVPR)”
• Section 2.7.1.5, “Interrupt Vector Offset Registers (IVORs)”
• Section 2.7.1.6, “Exception Syndrome Register (ESR)”
2.7.1.1 Save/Restore Register 0/1 (SRR0 and SRR1)
The e500 implements SRR0 and SRR1 as they are defined by the Book E architecture. On a
noncritical interrupt, SRR0 holds the address of the instruction where the interrupted process
should resume. The instruction is interrupt-specific, although for instruction-caused exceptions, it
is typically the address of the instruction that caused the interrupt. When rfi executes, instruction
execution continues at the address in SRR0.
SRR1 is provided to save and restore machine state on noncritical interrupts. When a noncritical
interrupt is taken, MSR contents are placed in SRR1. When rfi executes, SRR1 contents are placed
into MSR. SRR1 bits that correspond to reserved MSR bits are also reserved. These registers are
not affected by rfci or rfmci. Reserved MSR bits may be altered by rfi, rfci, or rfmci.
2.7.1.2 Critical Save/Restore Register 0/1 (CSRR0 and CSRR1)
The e500 implements CSRR0 and CSRR1 as they are defined by the Book E architecture. On a
critical interrupt, CSRR0 holds the address of the instruction where the interrupted process should
resume. The instruction is interrupt-specific, although for instruction-caused exceptions, it is
typically the address of the instruction that caused the interrupt. When rfci executes, instruction
execution continues at the address in CSRR0.
CSRR1 is provided to save and restore machine state on critical interrupts. When a critical
interrupt is taken, MSR contents are placed in CSRR1. When rfci executes, SRR1 contents are
placed into MSR. CSRR1 bits that correspond to reserved MSR bits are also reserved. These
registers are not affected by rfi or rfmci. Reserved MSR bits may be altered by rfi, rfci, or rfmci.
2.7.1.3 Data Exception Address Register (DEAR)
The e500 implements DEAR as it is defined by the Book E architecture. DEAR is loaded with the
effective address of a data access (caused by a load, store, or cache management instruction) that
results in an alignment, data TLB miss, or DSI exception.