Freescale Semiconductor PowerPC e500 Core - MAS Register 3 (MAS3)

Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-29
Figure 12-14 describes the format of MAS3. The core complex uses the same bit definitions as the
Freescale Book E standard for MAS3 for 32-bit implementations.
Table 12-11 shows the core complex MAS3 bit definitions.
61 M Memory coherence required
0 Memory coherence is not required.
1 Memory coherence is required. This allows loads and stores to this page to be coherent with loads
and stores from other processors (and devices) in the system, assuming all such devices are
participating in the coherence protocol.
62 G Guarded
0 Accesses to this page are not guarded and can be performed before it is known if they are
required by the sequential execution model.
1 All loads and stores to this page that miss in the L1 cache are performed without speculation (that
is, they are known to be required). Speculative loads can be performed if they hit in the L1 cache.
In addition, accesses to caching-inhibited pages are performed using only the memory element
that is explicitly specified.
63 E Endianness. Determines endianness for the corresponding page. Little-endian operation is true little
endian, which differs from the modified little-endian byte-ordering model optionally available in
previous devices that implement the original PowerPC architecture.
0 The page is accessed in big-endian byte order.
1 The page is accessed in true little-endian byte order.
SPR 627 Access: Supervisor-only
32 51 52 53 54 57 58 59 60 61 62 63
R
RPN — U0–U3 UX SX UW SW UR SR
W
Reset All zeros
Figure 12-14. MAS Register 3 (MAS3)
Table 12-11. MAS3 Field Descriptions–RPN and Access Control
Bits Name Description
32–51 RPN Real page number. Depending on page size, only the bits associated with a page boundary are valid.
Bits that represent offsets within a page are ignored and should be cleared. Note that, on the e500v2,
additional bits of the RPN are contained in MAS7. See Section 12.7.1.1, “MAS Register 7 (MAS7),” for
more information.
52–53 — Reserved, should be cleared.
54–57 U0–U3 User attribute bits. These bits are associated with a TLB entry and can be used by system software.
For example, these bits may be used to hold information useful to a page scanning algorithm or be
used to mark more abstract page attributes.
58–63 PERMIS Permission bits (UX, SX, UW, SW, UR, SR). User and supervisor read, write, and execute permission
bits. See the
EREF : . for more information on the page permission bits as they are defined by Book E.
Table 12-10. MAS2 Field Descriptions—EPN and Page Attributes (continued)
Bits Name Description