Freescale Semiconductor PowerPC e500 Core - E500 V2 Differences

Core Complex Overview
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 1-11
— Low-power design
— Power-saving modes: core-halted and core-stopped
— Internal clock multipliers ranging from 1 to 8 times the bus clock, including integer and
half-mode multipliers.
— Dynamic power management of execution units, caches, and MMUs
— NAP, DOZE, and SLEEP bits in HID0 can be used to assert nap, doze, and sleep output
signals to initiate power-saving modes at the integrated device level.
• Testability
— LSSD scan design
— JTAG interface
— ESP support
— Nexus debug support
• Reliability and serviceability
— Parity checking on caches
— Parity checking on e500 local bus
1.3.1 e500v2 Differences
The e500v2 provides the following additional features not supported by the e500v1:
• The e500v2 uses 36-bit physical addressing, which is supported by the following:
— MMU assist register 7 (MAS7)
— HID0[EN_MAS7_UPDATE]
— Programmable jumper options to specify the upper bits of the reset vector.
• The e500v2 has a 512-entry, 4-way set-associative unified TLB for TLB1.
• The maximum variable page size is extended to 4 Gbytes.
• Embedded double-precision floating-point APU has been added. These instructions use the
64-bit GPRs as single, 64-bit double-precision operands. This APU is enabled through
MSR[SPE].
• Slightly different functionality of HID1[RFXE] bit.
• The data line fill buffer in the LSU is expanded from three to five entries.
• The load miss queue in the LSU is expanded from four to nine entries.
• TBSEL and TBEE bits have been added to the performance monitor global control
register 0 (PMGC0) to support monitoring of time base events.
• Minor modifications to the SPE APU.