Freescale Semiconductor PowerPC e500 Core - The E500 Timer Implementation

Timer Facilities
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 9-3
and TCR[FPEXT]. The TCR controls decrementer, fixed-interval timer, and watchdog
timer options.
Section 2.6.1, “Timer Control Register (TCR),” describes the TCR in detail.
• Timer status register (TSR). Contains status on timer events and the most recent
watchdog-timer-initiated processor reset. Section 2.6.2, “Timer Status Register (TSR),”
describes the TSR in detail.
• Decrementer register (DEC). DEC contents can be read into bits 32–63 of a GPR using
mfspr, clearing bits 0–31. GPR contents can be written to the decrementer using mtspr.
See Section 2.6.4, “Decrementer Register (DEC),” for more information.
• Decrementer auto-reload register (DECAR). Supports the auto-reload feature of the
decrementer. The DECAR contents cannot be read. See Section 2.6.5, “Decrementer
Auto-Reload Register (DECAR),” for more information.
9.3 The e500 Timer Implementation
The clock source for the e500 timer facilities is specified by two fields in HID0: time base enable
(TBEN) and select time base clock (SEL_TBCLK). If HID0[TBEN] = 0, the time base is static;
there is no counting. If the time base is enabled (HID0[TBEN] is set), the clock source is
determined as follows:
• If HID0[SEL_TBCLK] = 0, the timer facilities are updated every 8 CCB clocks.
• If HID0[SEL_TBCLK] = 1, the timer facilities are updated on the rising edge of RTC.
The default source is the CCB clock divided by eight. For more details see Section 2.10.1,
“Hardware Implementation-Dependent Register 0 (HID0).”
• If HID0[TBEN] = 0, the time base is static (no counting)
• If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 0, the time base is updated every 8 bus
clocks
• If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 1, the time base is sampled at the bus rate;
that is, it is updated on the rising edge of tbclk. (Some implementations may use a signal
with a different name.) The maximum supported frequency can be found in the electrical
specifications, but this value is approximately 25% of the bus clock frequency.
The decrementer, TBL, and TBU are updated in that order during three successive internal
processor clock cycles.
The core output signals wrs
[0:1] reflect the value of TSR[WRS]. The intention is to signal to the
system that a watchdog reset event has occurred. The system can then implement a reset strategy.
The core can be reset by asserting hreset
. No automatic resetting is done when a watchdog reset
occurs.