PowerPC e500 Core Family Reference Manual, Rev. 1
9-4 Freescale Semiconductor
Timer Facilities
9.3.1 Alternate Time Base APU
The alternate time base APU defines a time base counter similar to the time base defined in
PowerPC architecture. It is intended to be used for measuring time in implementation-defined
intervals. It differs from the PowerPC defined time base in that it is not writable, it counts at a
different frequency, and it always counts up, wrapping when the 64-bit count overflows.
The alternate time base is a 64-bit counter that counts up at an implementation-dependent rate.
While not required, the rate is encouraged to be at the core clock frequency or as small a multiple
of the frequency as practical for the implementation. On the e500v2, this frequency is the core
frequency.
The ATBU and ATBL registers can be read by executing an mfspr instruction, but cannot be
written. Reading the ATB (or ATBL) register places the lower 32 bits of the counter into the target
register. A second SPR, ATBU, is defined that accesses only the upper 32 bits of the counter. Thus
the upper 32 bits of the counter may be read into a register by reading the ATBU register regardless
of computation mode.
The ATB registers are described in Section 2.6.6, “Alternate Time Base Registers (ATBL and
ATBU).”
The effect of power-savings mode or core frequency changes on counting in the alternate time base
is implementation dependent. See the User’s Manual for details.
9.3.2 Performance Monitor Time Base Event
The e500v2 has added the ability to count transitions of the TBL bit selected by PMGC0[TBSEL].
This count is enabled by setting PMGC0[TBEE]. For specific information, see Chapter 7,
“Performance Monitor.”
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