PowerPC e500 Core Family Reference Manual, Rev. 1
11-22 Freescale Semiconductor
L1 Caches
Lock bits in both caches are cleared automatically upon power-up. A subsequent reset operation
does not clear the lock bits automatically. Software must use the CLFC controls if flash clearing
of the lock bits is desired after a warm reset. Setting CLFC bits causes a flash invalidation
performed in a single CPU cycle, after which the CLFC bits are automatically cleared (CLFC bits
are not sticky).
11.5 L1 Data Cache Flushing
Any modified entries in the data cache can be copied back to memory (flushed) by using a dcbf
instruction or by executing a series of 12 uniquely addressed load or dcbz instructions to each of
the 128 sets. The address space should not be shared with any other process to prevent snoop hit
invalidations during the flushing routine. Exceptions should be disabled during this time so that
the PLRU algorithm is not disturbed.
The following methods can be used to flush a region in the L1 cache:
• Perform reads to any 48-Kbyte region, then execute dcbf instructions to that region. Note
that a 48-Kbyte region must be used to ensure that the PLRU algorithm flushes all of the
cache entries (12 x 128 sets x 32 bits = 48 Kbytes).
• Perform reads from any 48-Kbyte region that is guaranteed to not be modified in the L1
cache (for example, a ROM region).
• Execute dcbz instructions to any 48-Kbyte scratch section, then invalidate the cache. Note
that it is necessary to use a scratch region because some zeroed lines will be cast out.
For each of these methods, the following is necessary:
• Interrupts must be disabled.
• The 48-Kbyte region chosen is not being used by the system—that is, that snoops do not
occur to this region.
On the e500v2 the HID0 register contains a field, DCFA (data cache flush assist), that, when set,
forces the data cache to ignore invalid sets on miss replacement selection and follow the
replacement sequence defined by the PLRU bits. This reduces the series of uniquely addressed
load or dcbz instructions to eight per set. The bit should be set just before beginning a cache flush
routine and should be cleared when the series of instructions is complete.
11.6 L1 Cache Operation
This section describes operations performed by the L1 instruction and data caches.
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