Freescale Semiconductor PowerPC e500 Core - E500 Exception Priorities; E500 Interrupt Latency

Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-39
5.11.1 e500 Exception Priorities
The following is a prioritized listing of e500 exceptions:
1. HRESET (Note that hard reset is not defined as a true interrupt in Book E, but is included
here to show its relationship to the interrupt structure.)
2. Machine_check
3. Debug_ude_exc
4. Critical input
5. Debug interrupt
6. External input
7. Debug—trap | instruction address compare
8. ITLB miss
9. ISI
10.SPE/embedded floating-point APU unavailable
11. Program
12.DTLB miss
13.DSI
14.Alignment
15.Embedded floating-point data interrupt
16.Embedded floating-point round interrupt
17.System call
18.Debug—data address compare | branch taken | instruction compare | return from interrupt
19.Watchdog
20.Fixed interval timer
21.Performance monitor
22.Decrementer
5.12 e500 Interrupt Latency
Interrupt latency of the core complex is 8 cycles or less unless a guarded load or a cache-inhibited
stwcx. instruction is in the last completion queue entry (CQ0). For specific information, see
Section 4.3.4, “Interrupt Latency.”