Register Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 2-19
2.7.1.4 Interrupt Vector Prefix Register (IVPR)
The e500 implements IVPR as it is defined by the Book E architecture. It is used with IVORs to
determine the vector address. IVPR[32–47] provides the high-order 16 bits of the address of the
exception processing routines. The 16-bit vector offsets are concatenated to the right of
IVPR[32–47] to form the address of the exception processing routine.
2.7.1.5 Interrupt Vector Offset Registers (IVORs)
The e500 implements the IVORs as defined by the Book E architecture, but use only
IVORn[48–59], as shown in Figure 2-9, to hold the quad-word index from the base address
provided by the IVPR for each interrupt type.
Table 2-8 shows the IVORs implemented on the e500. IVOR0–IVOR15 are defined by the
architecture. (Note that the e500 does not implement IVOR7 and IVOR9.) In addition,
IVOR32–IVOR35 (SPR 528–531) are used by the e500 APUs.
SPR (See Tabl e 2 -8 .) Access: Supervisor-only
32 46 47 59 60 63
R
— Interrupt vector offset —
W
Reset All zeros
Figure 2-9. Interrupt Vector Offset Registers (IVORs)
Table 2-8. IVOR Assignments
IVOR Number SPR Interrupt Type
IVOR0 400 Critical input
IVOR1 401 Machine check
IVOR2 402 Data storage
IVOR3 403 Instruction storage
IVOR4 404 External input
IVOR5 405 Alignment
IVOR6 406 Program
IVOR7 407 Floating-point unavailable (Not supported on the e500)
IVOR8 408 System call
IVOR9 409 Auxiliary processor unavailable (Not supported on the e500)
IVOR10 410 Decrementer
IVOR11 411 Fixed-interval timer interrupt
IVOR12 412 Watchdog timer interrupt
IVOR13 413 Data TLB error
IVOR14 414 Instruction TLB error
IVOR15 415 Debug
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