Register Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 2-53
User-level PMRs in Table 2-37 are read-only and are accessed with mfpmr. Attempting to write
user-level registers in supervisor or user mode causes an illegal instruction exception.
2.15.1 Global Control Register 0 (PMGC0)
The performance monitor global control register (PMGC0), shown in Figure 2-39, controls all
performance monitor counters.
PMGC0 is cleared by a hard reset. Reading this register does not change its contents. Table 2-38
describes the PMGC0 fields.
Table 2-37. Performance Monitor Registers—User Level (Read-Only)
Abbreviation Register Name PMR Number pmr[0–4] pmr[5–9] Section/Page
UPMGC0 User performance monitor global control register 0 384 01100 00000 2.15.2/2-54
UPMLCa0 User performance monitor local control a0 128 00100 00000 2.15.4/2-56
UPMLCa1 User performance monitor local control a1 129 00100 00001
UPMLCa2 User performance monitor local control a2 130 00100 00010
UPMLCa3 User performance monitor local control a3 131 00100 00011
UPMLCb0 User performance monitor local control b0 256 01000 00000 2.15.6/2-57
UPMLCb1 User performance monitor local control b1 257 01000 00001
UPMLCb2 User performance monitor local control b2 258 01000 00010
UPMLCb3 User performance monitor local control b3 259 01000 00011
UPMC0 User performance monitor counter 0 0 00000 00000 2.15.8/2-58
UPMC1 User performance monitor counter 1 1 00000 00001
UPMC2 User performance monitor counter 2 2 00000 00010
UPMC3 User performance monitor counter 3 3 00000 00011
PMGC0 (PMR400)
UPMGC0 (PMR384)
Access: PMGC0: Supervisor-only
UPMGC0: Supervisor/user read-only
32 33 34 35 50 51 52 53 54 55 56 63
R
FAC PMIE FCECE — TBSEL
1
— TBEE
1
—
W
Reset All zeros
1
e500v2 only
Figure 2-39. Performance Monitor Global Control Register 0 (PMGC0)/
User Performance Monitor Global Control Register 0 (UPMGC0)
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