Freescale Semiconductor PowerPC e500 Core - Completion Groupings; Execution Unit Considerations; Serialization Effects; SU Considerations

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-47
Figure 4-2). The following list describes some of the common conditions that may cause
instructions to stall in the completion stage:
• A refetch-serialized instruction has generated a pending flush of the instruction pipeline.
• There are no finished instructions in the CQ.
• Only one store instruction can complete per cycle.
• A store cannot complete out of CQ1 if the instruction producing its data value is completing
out of CQ0 at the same time.
• Some instructions must complete out of CQ0.
• All refetch-serialized instructions except for isync must stall an extra cycle before
completing. This includes phantom branches, as described in Section 4.4.1.3.4, “BTB
Special Cases—Phantom Branches and Multiple Matches.”
• If the instruction in CQ0 is a refetch-serialized instruction, the entry in CQ1 should not be
considered valid.
• If the instruction in CQ0 is a mispredicted branch, the entry in CQ1 should not be
considered valid.
These and other less common conditions are described in the e500 Software Optimization Guide.
4.7.4.1 Completion Groupings
The e500 can retire as many as two instructions per cycle. Only two renames can be retired per
cycle. For example, an lwzu, add sequence has three GPR rename targets so both instructions
cannot retire in the same cycle. The lwzu is broken during decode into two parts, each of which
updates one rename. Both halves of the lwzu instruction can retire in one cycle. The add retires
1 cycle later.
4.7.5 Serialization Effects
The e500 supports the serialization described in Section 4.3.3.3, “Instruction Serialization.”
Tables in Section 4.6, “Instruction Latency Summary,” indicate which instructions require
serialization.
4.7.6 Execution Unit Considerations
The following sections describe how to optimize use of the execution units.
4.7.6.1 SU Considerations
Each SU has one reservation station in which instructions are held until operands are available.
Also note that some SU1 instructions take more than one cycle and that some are not fully