Freescale Semiconductor PowerPC e500 Core - Performance Monitor APU Registers

PowerPC e500 Core Family Reference Manual, Rev. 1
7-2 Freescale Semiconductor
Performance Monitor
• PMRs:
— The performance monitor counter registers (PMC0–PMC3) are 32-bit counters used to
count software-selectable events. Each counter counts up to 128 events.
UPMC0–UPMC3 provide user-level read access to these registers. Reference events are
those that should be applicable to most microprocessor microarchitectures and be of
general value. They are identified in Table 7-10.
— The performance monitor global control register (PMGC0) controls the counting of
performance monitor events. It takes priority over all other performance monitor control
registers. UPMGC0 provides user-level read access to PMGC0.
— The performance monitor local control registers (PMLCa0–PMLCa3,
PMLCb0–PMLCb3) control each individual performance monitor counter. Each
counter has a corresponding PMLCa and PMLCb register. UPMLCa0–UPMLCa3 and
UPMLCb0–UPMLCb3 provide user-level read access to PMLCa0–PMLCa3,
PMLCb0–PMLCb3).
• The performance monitor interrupt follows the Book E interrupt model and is assigned to
interrupt vector offset register 35 (IVOR35). Its priority is less than the fixed-interval
interrupt and greater than the decrementer interrupt.
Software communication with the performance monitor APU is achieved through PMRs rather
than SPRs. The PMRs are used for enabling conditions that can trigger a APU-defined
performance monitor interrupt.
7.2 Performance Monitor APU Registers
The performance monitor APU provides a set of PMRs for defining, enabling, and counting
conditions that trigger the performance interrupt. It also defines IVOR35 (SPR 531) for indicating
the address of the performance monitor interrupt vector. IVOR35 is described in Section 2.7.1.5,
“Interrupt Vector Offset Registers (IVORs).”
The supervisor-level performance monitor registers in Table 7-1 are accessed with mtpmr and
mfpmr. Attempting to read or write supervisor-level registers in user-mode causes a privilege
exception.
Table 7-1. Performance Monitor Registers–Supervisor Level
Number PMR[0–4] PMR[5–9] Name Abbreviation
16 00000 10000 Performance monitor counter 0 PMC0
17 00000 10001 Performance monitor counter 1 PMC1
18 00000 10010 Performance monitor counter 2 PMC2
19 00000 10011 Performance monitor counter 3 PMC3
144 00100 10000 Performance monitor local control a0 PMLCa0