PowerPC e500 Core Family Reference Manual, Rev. 1
11-28 Freescale Semiconductor
L1 Caches
11.7.2.1 L2 Unlocking
When the core complex executes an instruction (dcblc, icblc) to unlock an L2 cache line, it
performs the associated bus operation as an address-only transaction with a ttx encoding of
CLEAN and with the lock attribute asserted. An L2 cache may recognize this transaction as a
direction to unlock the specified address from its cache. This transaction always is performed as
non-global because it is specifically targeted at an L2 cache.
An L2 cache may also use other bus transactions to cause locks to be cleared, such as bus
transactions as a result of dcbf (identified on the bus as an address-only FLUSH, or as an L1 push
due to dcbf).
11.7.2.2 L1 Overlock
A program may attempt to establish a ninth locked entry at a cache index that already has all eight
of its ways locked. In this overlock case, the core complex performs a reading transaction on the
bus to initially bring in the ninth (newest) line and then immediately push that line out to bus as a
nonglobal burst write with the lock attribute asserted, rather than attempt to allocate that line in the
L1 data cache. This write operation looks identical on the bus to the hit-to-modified case described
in Section 11.7.2, “L2 Locking.”
To Next Page
Loading...
