Freescale Semiconductor PowerPC e500 Core - Dispatch, Issue, and Completion Considerations

PowerPC e500 Core Family Reference Manual, Rev. 1
4-14 Freescale Semiconductor
Execution Timing
4.3.3 Dispatch, Issue, and Completion Considerations
The core’s ability to dispatch as many as two instructions per cycle depends on the mix of
instructions and on the availability of issue queues and CQ entries. As many as two instructions
can be dispatched in parallel, but an instruction in IQ1 cannot be dispatched ahead of an instruction
in IQ0.
Instructions can issue out of order from GIQ0 and GIQ1. GIQ0 can issue to SU1, MU, and LSU.
GIQ1 can issue to SU2, MU, and LSU. If an instruction stalls in GIQ0 (reservation station busy),
an instruction in GIQ1 can issue if its reservation station is available.
Issue queues and reservation stations allow the e500 to dispatch instructions even if execution
units are busy. The issue logic reads operands from register files and rename registers and routes
instructions to the proper execution unit. Execution begins when all operands are available, the
instruction is in the reservation station, and any execution serialization requirements are met.
Instructions pass through a single-entry reservation station associated with each execution unit. If
a data dependency keeps an instruction from starting execution, that instruction is held in a
reservation station. Execution begins during the same clock cycle that the rename register is
updated with the data the instruction is dependent on.
The CQ maintains program order after instructions are dispatched, guaranteeing in-order
completion and a precise exception model. Instruction state and other information required for
completion are kept in this 14-entry FIFO. All instructions complete in order; none can retire
ahead of a previous instruction. In-order completion ensures the correct architectural state when
the e500 must recover from a mispredicted branch or exception.
Instructions are retired much as they are dispatched: as many as two can be retired simultaneously,
but never out of order. Note the following:
• Instructions must be non-speculative to complete.
• As many as two rename registers can be updated per clock cycle. Because load and store
with update instructions require two rename registers they are broken into two instructions
at dispatch (lwzu is broken into lwz and addi). As described in Section 4.3.3.1, “GPR and
CR Rename Register Operation,” these two instructions are assigned two CQ entries and
each is assigned CR and GPR renames at dispatch.
• Some instructions have retirement restrictions, such as retiring only out of CQ0. See
Section 4.3.3.3, “Instruction Serialization.”
Program-related exceptions are signaled when the instruction causing the exception reaches CQ0.
Previous instructions are allowed to complete before the exception is taken, which ensures that any
exceptions those instructions may cause are taken.