PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 2-1
Chapter 2
Register Model
This chapter describes implementation-specific details of the register model as it is implemented
on the e500 core processors. It identifies all registers that are implemented on the e500 cores, but,
with a few exceptions, does not include full descriptions of those registers and register fields that
are implemented exactly as they are defined by the Book E architecture and by the Freescale
Book E implementation standards (EIS). A full description of these registers is provided in the
EREF: A Reference for Freescale Book E and the e500 Core (EREF).
It is important to note that a device that integrates the e500 core may not implement all of the fields
and registers that are defined here, and may interpret some fields more specifically than can be
defined here. For specific details, refer to the “Register Summary” chapter in the reference manual
for the device that incorporates the e500 core. The register summary chapter fully describes all
registers and register fields as they are implemented on the device.
2.1 Overview
Although this chapter organizes registers according to their functionality, they can be
differentiated according to how they are accessed, as follows:
• General-purpose registers (GPRs)—Used as source and destination operands for most
operations. The e500 implements 64-bit GPRs. Book E–defined instructions access only
the lower word; SPE vector instructions and embedded vector single-precision and
double-precision floating-point APUs (e500v2 only) use all 64 bits. See Section 2.3.1,
“General-Purpose Registers (GPRs).”
• Special-purpose registers (SPRs)—Accessed by using the Book E–defined Move to
Special-Purpose Register (mtspr) and Move from Special-Purpose Register (mfspr)
instructions. Section 2.2.1, “Special-Purpose Registers (SPRs),” lists SPRs.
• System-level registers that are not SPRs. These are as follows:
— Machine state register (MSR). MSR is accessed with the Move to Machine State
Register (mtmsr) and Move from Machine State Register (mfmsr) instructions. See
Section 2.5.1, “Machine State Register (MSR).”
— Condition register (CR) bits are grouped into eight 4-bit fields, CR0–CR7, which are set
as follows:
– Specified CR fields can be set by a move to the CR from a GPR (mtcrf).
– A specified CR field can be set by a move to the CR from another CR field (mcrf),
or from the XER (mcrxr).
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