PowerPC e500 Core Family Reference Manual, Rev. 1
4-16 Freescale Semiconductor
Execution Timing
• Move-to serialization—A move-to serialized instruction cannot execute until the cycle
after it is in CQ0, that is, the cycle after it becomes the oldest instruction. This serialization
is weaker than move-from serialization in that the instruction need not spend an extra cycle
in the reservation station. Move-to serializing instructions include tlbre, tlbsx, tlbwe,
mtmsr, wrtee, wrteei, and all mtspr instructions.
• Refetch serialization—Refetch-serialized instructions force refetching of subsequent
instructions after completion. Refetch serialization is used when an instruction has changed
or may change a particular context needed by subsequent instructions. Examples include
isync, sc, rfi, rfci, rfmci, and any instruction that toggles the summary-overflow (SO) bit.
• Store serialization (applicable to stores and some LSU instructions that access the data
cache)—Store-serialized instructions are dispatched and held in the LSU’s finished store
queue. They are not committed to memory until all prior instructions have completed.
Although a store-serialized instruction waits in the finished store queue, other load/store
instructions can be freely executed. Some store-serialized instructions are further restricted
to complete only from CQ0. Only one store-serialized instruction can complete per cycle,
although non-serialized instructions can complete in the same cycle as a store-serialized
instruction. In general, all stores and cache operation instructions are store serialized.
4.3.4 Interrupt Latency
The e500v1 flushes all instructions in the completion queue when an interrupt is taken, except for
guarded load or cache-inhibited stwcx. instructions in CQ0.
Core complex interrupt latency (the number of core clocks between the sampling of the interrupt
signal as asserted and the fetch of the first instruction in the handler) is at most 8 cycles unless a
guarded load or a cache-inhibited stwcx. is in CQ0. This latency does not include the 2 bus cycles
needed to synchronize the interrupt signal from the pad of the device. When an interrupt is
detected, only guarded load and cache-inhibited stwcx. instructions in CQ0 are allowed to
complete; in such cases, interrupt latency is affected by bus latency.
Note that a load instruction that misses in the cache may generate a bus read operation, even
though the load instruction does not complete because of an interrupt. In this case, data is returned
to the line fill buffer and the cache line is updated, but not the GPR specified by the load
instruction. When the same load is executed again, the load is performed again, most likely from
the cache or from the line fill buffer, and the GPR write back occurs after the instruction completes
and is deallocated from CQ0.
On the e500v2, if an interrupt is asserted during a guarded load (that misses in the L1 cache) or a
caching-inhibited stwcx., the interrupt is not taken until the instruction completes. So, the interrupt
latency depends on the memory latency.
• For guarded loads, the data must be returned. If a bus error occurs on a guarded load, the
load is aborted and the interrupt is taken.
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