Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-25
Instruction execution resumes at address IVPR[32–47] || IVOR6[48–59] || 0b0000.
5.7.8 System Call Interrupt
A system call interrupt occurs when no higher priority exception exists and a System Call (sc)
instruction is executed. SRR0, SRR1, and MSR are updated as shown in Table 5-19.
Instruction execution resumes at address IVPR[32–47] || IVOR8[48–59] || 0b0000.
5.7.9 Decrementer Interrupt
A decrementer interrupt occurs when no higher priority exception exists, a decrementer exception
exists (TSR[DIS] = 1), and the interrupt is enabled (TCR[DIE] = 1 and MSR[EE] = 1).
NOTE
MSR[EE] also enables external input and fixed-interval timer
interrupts.
SRR0, SRR1, MSR, and TSR are updated as shown in Table 5-20.
Instruction execution resumes at address IVPR[32–47] || IVOR10[48–59] || 0b0000.
MSR CE, ME, and DE are unchanged. All other MSR bits are cleared.
ESR PIL Set if an illegal instruction exception-type program interrupt; otherwise cleared.
PPR Set if a privileged instruction exception-type program interrupt; otherwise cleared.
PTR Set if a trap exception-type program interrupt; otherwise cleared.
All other defined ESR bits are cleared.
Table 5-19. System Call Interrupt Register Settings
Register Description
SRR0 Set to the effective address of the instruction after the sc instruction.
SRR1 Set to the MSR contents at the time of the interrupt.
MSR CE, ME, and DE are unchanged. All other MSR bits are cleared.
Table 5-20. Decrementer Interrupt Register Settings
Register Setting
SRR0 Set to the effective address of the next instruction to be executed.
SRR1 Set to the MSR contents at the time of the interrupt.
MSR CE, ME, and DE are unchanged. All other MSR bits are cleared.
TSR DIS is set.
Table 5-18. Program Interrupt Register Settings (continued)
Register Description
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