PowerPC e500 Core Family Reference Manual, Rev. 1
5-40 Freescale Semiconductor
Interrupts and Exceptions
5.13 Guarded Load and Cache-Inhibited stwcx.
Instructions
The e500v2 does not service an interrupt (including machine check) if a guarded load or
cache-inhibited stwcx. is pending, but if bus errors occur, the load or stwcx. instruction may never
complete.
If a guarded load gets a bus error, the guarded attribute is cleared on the load. Note that a guarded
load cannot go out on the bus until it reaches the bottom of the completion queue (CQ), so only a
guarded load in the bottom of the completion queue (CQ0) can get a bus error. When a load hits
bad data in the line-fill buffer, lac_ldst_finish is squashed (as described above), but
lac_clear_guarded is asserted in its place (along with the tag). If the tag of CQ0 matches the
load/store tag when lac_clear_guarded is asserted, the guarded attribute in CQ0 is cleared.
This process allows the completion unit to take an interrupt. If a cache-inhibited stwcx. gets an
address error, the action taken is effectively the same as what happens if a snoop causes the loss
of the reservation. The reservation is cleared, and the cache-inhibited stwcx. finishes and reports
CR = 0, indicating that the stwcx. did not succeed. This allows the stwcx. to complete and the
completion unit can then take an interrupt.
Note the following:
• This implementation does not make address errors precache-inhibited for cache-inhibited
stwcx., as they are for loads. However, if the stwcx. failed due to an was an address error,
the software is likely to spin in the lwarx/stwcx. loop until an interrupt occurs. Bus errors
on other stores are not precise either.
• Because a cache-inhibited stwcx. finishes as soon as the address tenure completes, there is
no concern about hanging a cache-inhibited stwcx. in completion due to a write bus data
error.
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