Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-37
5.10.2 Interrupt Order
Enabled interrupt types for which simultaneous exceptions can exist are prioritized as follows:
1. Synchronous (non-debug) interrupts:
— Data storage
— Instruction storage
— Alignment
— Program
— System call
— Data TLB error
— Instruction TLB error
Only one of the above synchronous interrupt types may have an existing exception
generating it at a given time. This is guaranteed by the exception priority mechanism (see
Section 5.11, “Exception Priorities”) and the sequential execution model.
2. Machine check
3. Debug
4. Critical input
5. Watchdog timer
6. External input
7. Fixed-interval timer
8. Decrementer
Although, as indicated above, noncritical, synchronous exception types listed under item 1 are
generated with higher priority than critical interrupt types in items 2–5, noncritical interrupts are
immediately followed by the highest priority existing critical interrupt type, without executing any
instructions at the noncritical interrupt handler. This is because noncritical interrupt types do not
automatically disable MSR mask bits for critical interrupt types (CE and ME). In all other cases,
a particular interrupt type listed above automatically disables subsequent interrupts of the same
type, as well as all lower priority interrupt types.
5.11 Exception Priorities
Book E requires all synchronous (precise and imprecise) interrupts to be reported in program
order, as required by the sequential execution model. The one exception to this rule is the case of
multiple synchronous imprecise interrupts. Upon a synchronizing event, all previously executed
instructions are required to report any synchronous imprecise interrupt-generating exceptions, and
the interrupt is then generated with all of those exception types reported cumulatively in the ESR
and in any status registers associated with the particular exception type (such as the SPEFSCR).
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