Freescale Semiconductor PowerPC e500 Core - SPE Operands: Signed Fractions

Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-51
are written with the result of the vector compare, one for each element. The two defined bits could
be used either by a vector select instruction or by a UISA branch instruction.
A partially visible accumulator register is architected for the integer and fractional multiply
accumulate SPE instructions. It is described in Section 2.14.2, “Accumulator (ACC).”
Full descriptions of these instructions can be found in the “Instruction Set” chapter of the EREF.
3.8.1.1 SPE Operands: Signed Fractions
In signed fractional format, the N-bit operand is represented in a 1.[N–1] format (1 sign bit, N–1
fraction bits). Signed fractional numbers are in the following range:
The real value of the binary operand SF[0:N–1] is as follows:
The most negative and positive numbers representable in fractional format are as follows:
• The most negative number is represented by SF(0) = 1 and SF[1:N–1] = 0 (that is, N=32;
0x8000_0000 = –1.0).
• The most positive number is represented by SF(0) = 0 and SF[1:N–1] = all 1s (that is, N=32;
0x7FFF_FFFF = 1.0 – 2
–(N–1)
).
1.0 SF 1.0 2
N1–()–
–≤≤–
SF 1.0 SF 0()•–=SFi() 2
i–
•
i1=
N1–
∑
+