Freescale Semiconductor PowerPC e500 Core - Unsupported Book E Instructions

Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-3
These instructions are described in Section 3.8.1.4, “Embedded Floating-Point APU Instructions.”
Unlike the PowerPC UISA, the SPFP APUs store floating-point operands as single-precision
values in true 32-bit, single-precision format rather than in a 64-bit double-precision format used
with FPRs.
NOTE
The SPE APU and embedded floating-point APU functionality is
implemented in all PowerQUICC III devices. However, these
instructions will not be supported in devices subsequent to
PowerQUICC III. Freescale Semiconductor strongly recommends
that use of these instructions be confined to libraries and device
drivers. Customer software that uses SPE or embedded floating-point
APU instructions at the assembly level or that uses SPE intrinsics will
require rewriting for upward compatibility with next-generation
PowerQUICC devices.
Freescale Semiconductor offers a libmoto_e500 library that uses SPE
instructions. Freescale will also provide libraries to support
next-generation PowerQUICC devices..
3.1.4 Unsupported Book E Instructions
Because the e500 core complex uses a 32-bit Book E core, all of the instructions defined only for
64-bit implementations of the Book E architecture are illegal in the e500. These instructions are
not listed in Table 3-2. The e500 core complex takes an illegal instruction exception-type program
interrupt upon encountering a 64-bit Book E instruction.
NOTE
Extended addressing forms of all load and store instructions are illegal
because they calculate a 64-bit effective address. Also, except for
certain vector instructions, all double-word instruction forms are illegal
because only 64-bit implementations allow double-word operands.
The e500 does not support the Book E instructions listed in Table 3-2. An illegal instruction
exception is generated if the processor attempts to execute one of these instructions. Some
instructions have the following optional features indicated by square brackets:
• Condition register (CR) update—The dot (.) suffix on the mnemonic enables the update of
the CR.
• Overflow option—The o suffix indicates that the overflow bit in the XER is enabled.