Freescale Semiconductor PowerPC e500 Core - Branch Completion (LR;CTR Write-Back)

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-19
Branch instructions are dispatched to the BIQ and are assigned a CQ slot, as shown in Figure 4-6.
Figure 4-6. Branch Completion (LR/CTR Write-Back)
In this example, the bc depends on cmp and is predicted as not taken. At the end of clock cycle 1,
cmp and bc are dispatched to the GIQ and BIQ, respectively, and are issued to SU1 and the BU at
the end of clock 2.
In clock cycle 3, the cmp executes in SU1 but the bc cannot resolve and complete until the cmp
results are available; add1 and add2 are dispatched to the GIQ.
In cycle 4, the bc resolves as correctly predicted; add1 and add2 are issued to the SUs and are
marked as nonspeculative, and add3 is dispatched to the GIQ. The cmp is retired from the CQ at
the end of cycle 4.
In cycle 5, bc, add1, and add2 finish execution, and bc and add1 retire.
Clock 1 Clock 2 Clock 3 Clock 4 Clock 5
IQ11
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IQ6
IQ5
IQ4 add3
IQ3 add2
IQ2 add1 add3
IQ1 bc add2
IQ0 cmp add1 add3
BIQ1
BIQ0 bc
GIQ3
GIQ2
GIQ1 add2
GIQ0 cmp add1 add3
CQ13
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CQ6
CQ5
CQ4
CQ3 add2 add2 (SU2) add3 (SU1)
CQ2 add1 add1 (SU1) add2√
CQ1 bc bc (BU) bc (BU) add1√
CQ0 cmp cmp (SU1) cmp√ bc √
√ indicates that the instruction has finished execution.