Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-27
5.7.11 Watchdog Timer Interrupt
A watchdog timer interrupt occurs when no higher priority exception exists, a watchdog timer
exception exists (TSR[WIS] = 1), and the interrupt is enabled (TCR[WIE] = 1 and MSR[CE] = 1).
The “Timers” chapter in the EREF describes Book E and EIS aspects of the watchdog timer.
NOTE
MSR[CE] also enables the critical input interrupt.
CSRR0, CSRR1, MSR, and TSR are updated as shown in Table 5-22.
Instruction execution resumes at address IVPR[32–47] || IVOR12[48–59] || 0b0000.
NOTE
To avoid redundant watchdog timer interrupts, before reenabling
MSR[CE], the interrupt handling routine must clear TSR[WIS] by
writing a word to TSR using mtspr with a 1 in any bit position to be
cleared and 0 in all others. The data written to the TSR is not direct
data, but a mask. Writing a 1 to this bit causes it to be cleared; writing
a 0 has no effect.
5.7.12 Data TLB Error Interrupt
A data TLB error interrupt occurs when no higher priority exception exists and the exception
described in Table 5-23 is presented to the interrupt mechanism.
If a store conditional instruction produces an effective address for which a normal store would
cause a data TLB error interrupt, but the processor does not have the reservation from a load and
reserve instruction, Book E defines it as implementation-dependent whether a data TLB error
interrupt occurs. The EIS defines that the interrupt is taken.
Table 5-22. Watchdog Timer Interrupt Register Settings
Register Setting
CSRR0 Set to the effective address of the next instruction to be executed.
CSRR1 Set to the MSR contents at the time of the interrupt.
MSR ME is unchanged; all other MSR bits are cleared.
TSR WIS is set.
Table 5-23. Data TLB Error Interrupt Exception Conditions
Exception Description
Data TLB miss exception Virtual addresses associated with a data fetch do not match any valid TLB entry.
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