Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-49
3.8.1 SPE and Embedded Floating-Point APUs
The e500 core complex provides a GPR file with 32, 64-bit registers. The 32-bit Book E
instructions operate on the lower (least-significant) 32 bits of the 64-bit register. SPE APU vector
instructions and embedded vector SPFP instructions treat 64-bit registers as containing two 32-bit
elements or four 16-bit elements as described in Section 3.8.1.3, “SPE APU Instructions.”
However, like 32-bit Book E instructions, scalar SPFP APU floating-point instructions use bits
32–63 of the GPRs to hold 32-bit single-precision operands, as described in Section 3.8.1.4,
“Embedded Floating-Point APU Instructions.”
The embedded double-precision floating-point APU (e500v2 only) uses the 64-bit GPRs to hold
64-bit, double-precision operands.
Figure 3-4 shows how the SPE and floating-point APU programming models compare, indicating
how each APU uses the GPRs.
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