Freescale Semiconductor PowerPC e500 Core - Instruction Set Summary

Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-5
3.2 Instruction Set Summary
This chapter describes instructions and addressing modes defined for the e500. These instructions
are divided into the following functional categories:
• Integer instructions—These include arithmetic and logical instructions. For more
information, see Section 3.3.1.1, “Integer Instructions.”
• Floating-point instructions—These include floating-point vector and scalar arithmetic
instructions. See Section 3.8.1.4, “Embedded Floating-Point APU Instructions.” The e500
does not support Book E–defined floating-point instructions or floating-point registers.
• Load and store instructions— See Section 3.3.1.2, “Load and Store Instructions.”
• Flow control instructions—These include branching instructions, CR logical instructions,
trap instructions, and other instructions that affect the instruction flow. See Section 3.3.1.3,
“Branch and Flow Control Instructions.”
• Processor control instructions—These instructions are used for synchronizing memory
accesses. See Section 3.3.1.5, “Processor Control Instructions.”
• Memory synchronization instructions—These instructions are used for memory
synchronizing. See Section 3.3.1.6, “Memory Synchronization Instructions.”
• Memory control instructions—These instructions provide control of caches and TLBs. See
Section 3.3.1.8, “Memory Control Instructions,” and Section 3.3.2.2, “Supervisor-Level
Memory Control Instructions.”
• Signal processing instructions—These include a set of vector arithmetic and logic
instructions optimized for signal processing tasks. See Section 3.8.1, “SPE and Embedded
Floating-Point APUs.”
Note that instruction groupings used here do not indicate the execution unit that processes a
particular instruction or group of instructions. This information, which is useful for scheduling
instructions most effectively, is provided in Chapter 4, “Execution Timing.”
Integer instructions operate on word operands. The PowerPC architecture uses instructions that are
4 bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores
between memory and a set of 32 general-purpose registers (GPRs).
Store Floating-Point as Integer Word Indexed stfiwx
Store Floating-Point Single [with Update] [Indexed] stfs[u][x]
Store String Word Immediate stswi
Store String Word Indexed stswx
Table 3-2. Unsupported Book E Instructions (32-Bit) (continued)
Name Mnemonic