PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 1-1
Chapter 1
Core Complex Overview
This chapter provides an overview of the PowerPC™ e500 microprocessor core.
References to e500 are true for both the e500v1 and e500v2.
This chapter includes the following:
• An overview of the Book E version of the PowerPC architecture features as implemented
in this core and a summary of the core feature set
• A summary of the instruction pipeline and flow
• An overview of the programming model
• An overview of interrupts and exception handling
• A description of the memory management architecture
• High-level details of the e500 core memory and coherency model
• A brief description of the core complex bus (CCB)
• A summary of the Book E architecture compatibility and migration from the original
version of the PowerPC architecture as it is defined by Apple, IBM, and Motorola (referred
to as the AIM version of the PowerPC architecture)
The e500 core provides features that the integrated device may not implement or may implement
in a more specific way.
1.1 Overview
The e500 processor core is a low-power implementation of the family of reduced instruction set
computing (RISC) embedded processors that implement the Book E definition of the PowerPC
architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words
in the 64-bit general-purpose registers (GPRs).
Figure 1-1 is a block diagram of the processor core complex that shows how the functional units
operate independently and in parallel. Note that this conceptual diagram does not attempt to show
how these features are physically implemented.
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