Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-37
dynamically allocate aligned and padded memory for locks to guarantee absence of
granularity-induced reservation loss.
3.3.1.8 Memory Control Instructions
Memory control instructions can be classified as follows:
• User- and supervisor-level cache management instructions.
• Supervisor-level–only translation lookaside buffer management instructions
This section describes the user-level cache management instructions. See Section 3.3.2.2,
“Supervisor-Level Memory Control Instructions,” for information about supervisor-level cache
and translation lookaside buffer management instructions.
This section does not describe the cache-locking APU instructions, which are described in
Section 3.8.4, “Cache Locking APU.”
3.3.1.8.1 User-Level Cache Instructions
The instructions listed in Table 3-26 help user-level programs manage on-chip caches if they are
implemented. See Chapter 11, “L1 Caches,” for more information about cache topics. The
following sections describe how these operations are treated with respect to the e500’s caches. The
e500 supports the following CT values, defined by the EIS:
• CT = 0 indicates the L1 cache.
• CT = 1 indicates the L2 cache.
As with other memory-related instructions, the effects of cache management instructions on
memory are weakly-ordered. If the programmer must ensure that cache or other instructions have
been performed with respect to all other processors and system mechanisms, an msync must be
placed after those instructions.
Note that the e500 interprets cache control instructions (icbi, dcbi, dcbf, dcbz, and dcbst) as if
they pertain only to local caches. On some implementations, HID1[ABE] must be set to allow
management of external L2 caches as well as other L1 caches in the system.
Section 3.8.4, “Cache Locking APU,” describes cache-locking APU instructions.
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