Freescale Semiconductor PowerPC e500 Core - Export Shared Memory and Release Lock Using Mbar (MO = 0); Safe Fetch; Update Instructions

Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-47
3.5.1.3.2 Export Shared Memory and Release Lock using mbar (MO = 0)
If both the lock and the shared data structure are in memory that is neither caching inhibited nor
write-through required, an mbar (MO = 0) instruction can be used as the export barrier. Using mbar rather
than msync yields better performance in most systems.
In this example it is assumed that both the lock and the shared data structure are in memory that is neither
caching inhibited nor write-through required, the address of the lock is in GPR 3, the value indicating that
the lock is free is in GPR 4, and the address of the shared data structure is in GPR 9.
stw r7,data1(r9) #store shared data (last)
mbar 0 #export barrier
stw r4,lock(r3) #release lock
The mbar (MO = 0) ensures that the store that releases the lock is not performed with respect to any other
processor until all stores caused by instructions preceding the mbar have been performed with respect to
that processor.
Recall that, for memory that is neither caching inhibited nor write-through required, mbar orders only
stores and has no effect on loads. If the portion of the program preceding the mbar contains loads from
the shared data structure and the stores to the shared data structure do not depend on the values returned
by those loads, the store that releases the lock could be performed before those loads. If it is necessary to
ensure that those loads are performed before the store that releases the lock, the programmer can either use
the msync instruction as in Section 3.5.1.3.1, “Export Shared Memory and Release Lock,” or use the
technique described in Section 3.5.2, “Safe Fetch.”
3.5.2 Safe Fetch
If a load must be performed before a subsequent store (for example, the store that releases a lock protecting
a shared data structure), a technique similar to the following can be used.
In this example it is assumed that the address of the memory operand to be loaded is in GPR 3, the contents
of the memory operand are returned in GPR 4, and the address of the memory operand to be stored is in
GPR 5.
lwz r4,0(r3) #load shared data
cmp cr0,0,r4,r4 #set CR0 to ‘equal’
bc 4,2,$-8 #branch never taken
stw r7,0(r5) #store other shared data
Alternatively, a technique similar to that described in Section 3.5.1.2, “Obtain Pointer and Import Shared
Memory,” can be used, by causing the stw to depend on the value returned by the lwz and omitting the
cmp and bc. The dependency could be created by ANDing the value returned by the lwz with zero and
then adding the result to the value to be stored by the stw.
3.6 Update Instructions
Load-with-update and store-with-update instructions are described in Book E. Internally, the e500
breaks these instructions into two sub-instructions. The update portion of the instruction is
executed by one of the simple units, and the load portion is executed by the load/store unit.