Freescale Semiconductor PowerPC e500 Core - Instruction Address Compare Debug Event; Instruction Address Compare User and Supervisor Modes

Debug Support
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 8-7
If interrupts are disabled, some debug events are not recorded; that is, no DBSR bit is set by the
event. However, some debug events can cause exceptions and set DBSR bits regardless of the state
of MSR[DE]. Interrupts resulting from such exceptions are delayed until MSR[DE] is set (unless
they have been cleared from the DBSR in the meantime).
Any time a DBSR bit can be set while MSR[DE] is cleared, the imprecise debug event bit
(DBSR[IDE]) is also set. IDE indicates whether the associated DBSR bit was set while debug
interrupts were disabled. Debug interrupt handler software can use this bit to interpret the address
in CSRR0. If IDE is zero, CSRR0 holds the address of the instruction causing the debug exception;
otherwise, it holds the address of the instruction following the one that enabled the delayed debug
interrupt.
Debug exceptions are prioritized with respect to other exceptions (see Section 5.11.1, “e500
Exception Priorities”).
Table 8-6 lists the types of debug events, which are discussed in subsequent sections.
8.4.1 Instruction Address Compare Debug Event
One or more instruction address compare debug events (IAC1 and IAC2) occur if they are enabled
and execution is attempted of an instruction at an address that meets the criteria specified in
DBCR0, DBCR1, and the IAC registers.
8.4.1.1 Instruction Address Compare User and Supervisor Modes
The debug control registers specify user and supervisor modes as follows:
• DBCR1[IAC1US] specifies whether IAC1 debug events can occur in user mode, in
supervisor mode, or in both.
• DBCR1[IAC2US] specifies whether IAC2 debug events can occur in user mode, in
supervisor mode, or in both.
Table 8-6. Debug Events
Event Type Description Section
Instruction address
compare
Each instruction address is compared in a specific way with a specific value. A debug
event occurs when they match.
8.4.1
Data address compare Each data address is compared with a value. A debug event occurs when they match. 8.4.2
Trap A debug event occurs when a trap is set. 8.4.3
Branch taken A debug event occurs when any branch is taken. 8.4.4
Instruction complete A debug event occurs when any instruction completes. 8.4.5
Interrupt taken A debug event occurs when an interrupt is taken. 8.4.6
Return A debug event occurs when a return from interrupt occurs. 8.4.7
Unconditional A debug event occurs whenever this instruction is executed. 8.4.8