Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-31
3.3.1.6.1 mbar (MO = 1)
As defined by the EIS, mbar (MO = 1) is functions like eieio, as it is defined by the Classic
PowerPC architecture. It provides ordering for the effects of load and store instructions. These
instructions consist of two sets, which are ordered separately. Memory accesses caused by a dcbz
or a dcba are ordered like a store. The two sets follow:
• Caching-inhibited, guarded loads and stores to memory and write-through-required stores
to memory. mbar (MO = 1) controls the order in which accesses are performed in main
memory. It ensures that all applicable memory accesses caused by instructions preceding
the mbar have completed with respect to main memory before any such accesses caused
by instructions following mbar access main memory. It acts like a barrier that flows
through the memory queues and to main memory, preventing the reordering of memory
accesses across the barrier. No ordering is performed for dcbz if the instruction causes the
system alignment error handler to be invoked.
Memory
Synchronize
msync — msync provides a memory barrier throughout the memory hierarchy. In the e500, msync
waits for proceeding data memory accesses to become visible to the entire memory
hierarchy; then it is broadcast on the bus. msync completes only after its address tenure
is performed without being ARTRYed. Subsequent instructions can execute out of order but
complete only after the msync completes.
msync latency depends on the processor state when it is dispatched and on various
system-level conditions. Frequent use of msync degrades performance.
System designs with an external cache should take care to recognize the hardware
signaling caused by an MSYNC bus operation and perform the appropriate actions to
guarantee that memory references that can be queued internally to the external cache have
been performed globally.
Note the following:
• msync is used to ensure that all stores into a data structure caused by store instructions
executed in a critical section of a program are performed with respect to another
processor before the store that releases the lock is performed with respect to that
processor. mbar is preferable in many cases.
• The Freescale EIS further requires that, unlike a context-synchronizing operation,
msync does not discard prefetched instructions.
The e500 broadcasts mbar only if ABE = 1 to allow management of external L2 caches and
other L1 caches in the system.
Section 3.5.1, “Lock Acquisition and Import Barriers,” describes how the msync and mbar
instructions can be used to control memory access ordering when memory is shared
between programs.
Store Word
Conditional
Indexed
stwcx. rS,rA,rB lwarx with stwcx. can emulate semaphore operations such as test and set, compare and
swap, exchange memory, and fetch and add. Both instructions must use the same EA.
Reservation granularity is implementation-dependent. The e500 makes reservations on
behalf of aligned 32-byte sections of address space. Executing lwarx and stwcx. to a page
marked write-through (WIMG = 10
xx
) or when the data cache is locked causes a data
storage interrupt. If the location is not word-aligned, an alignment interrupt occurs.
See Section 3.3.1.7, “Atomic Update Primitives Using lwarx and stwcx..”
Table 3-25. Memory Synchronization Instructions (continued)
Name Mnemonic Syntax Implementation Notes
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