Freescale Semiconductor PowerPC e500 Core - BTB Locking

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-23
Note that branch instructions that are not allocated into the BTB (either because they have never
been taken or because they have been cast out of the BTB) can fall in the same fetch group. For
example, the following code sequence has two branch instructions that fall into the same fetch
group the first time the sequence is executed:
A: add
b1
A+8: add
b2
Assuming that fetching begins at A and that the sequence lies within a cache block, all four
instructions are included in the same fetch group, including both branches because they have not
been taken and therefore do not have BTB entries.
At execution, b1 is not taken, but b2 mispredicts and resolves as taken in the execute stage, at
which point the branch instruction prediction (strongly taken) is allocated for b2 at A for the fetch
group address of A.
Later, b1 is taken and thus mispredicted. The BTB entry for address A becomes allocated for b1,
replacing the prediction for b2 for the FGA of A. If we fetch b2 again using the FGA of (A+8), it
is now a BTB miss and the default prediction is used. However, if the default prediction is
incorrect, a separate BTB entry is allocated for b2 (at fetch group address A+8).
Now that both branch instructions are allocated in the BTB, they can no longer be in the same fetch
group.
4.4.1.3.1 BTB Locking
Note that rather than allowing branch predictions to change dynamically, the programmer can
explicitly lock the predictions into the BTB.
The typical sequence of instructions to lock a branch address into a BTB entry is as follows:
mtspr BBEAR, rS
mtspr BBTAR, rS
bblels
The typical sequence of instructions to clear locked entries individually is as follows:
mtspr BBEAR, rS
bbelr
To guarantee atomicity, these instruction sequences should be protected by lwarx and stwcx.
instructions.