Core Complex Bus (CCB)
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 13-9
by tt[0:4] code and/or address decoding). By implementing such an operation directly in the
memory system, a system may avoid the problems of having to lock multiple bus transactions by
a processor throughout the system hierarchy, such as is typically done with the traditional LOCK
pin of other bus protocols.
An example of a system-defined atomic operation that could be implemented directly in the
memory system is an atomic set. For this operation, the memory system recognizes a unique read
transaction on the bus, returns the read data from the specified field in memory, and then
atomically writes the specified field to all ones. The field in memory might represent a high-true
semaphore flag to indicate that a resource has been claimed. The atomic-set operation (as well as
atomic-clear, atomic-increment, and atomic-decrement) is also defined for the RapidIO bus
protocol.
The triggering of such an atomic transaction could be done, for instance, by the READ-atomic
tt[0:4] code for a non-burst read, which occurs exclusively by the core complex for a
cache-inhibited lwarx, or it could be triggered by simple address decoding or other mechanisms.
Note that use of cache-inhibited lwarx would allow mixing of regular reads with atomic reads in
a memory system for robustness; however, because it is not compatible with the usual
lwarx/stwcx. behavior defined by the PowerPC architecture, such use would have to be carefully
controlled by the system.
13.7 Remote Atomic Status Monitoring
For system convenience, the core complex provides a system-defined atomic status bit
HID1[ATS] that a system may use for remote reservation management. If supported by the system,
this bit could be monitored by a program internally until an atomic location in the memory system
has been altered or cleared, thereby eliminating the bus bandwidth typically consumed by spinning
on the bus waiting for the release of a semaphore as in traditional systems. This bit is automatically
set whenever the core complex performs a lwarx(CI) transaction on the CCB. The memory system
can clear this bit by asserting the atomic status clear (ATSC) input to the CCB according to a
system-defined event. Such an event could be a write to a page of semaphore bits, indicating that
a semaphore in the system has been released and that each processor may then attempt to claim a
semaphore it is targeting.
13.8 Proper Reporting of Bus Faults
Except for one case in the e500v1 (described in the HID1[RFXE] bit description of Section 2.10.2,
“Hardware Implementation-Dependent Register 1 (HID1)), the following applies for bus faults in
the e500 core. When a bus fault is detected on a CCB transaction through the assertion of
core_fault_in
(and HID1[RFXE] = 0), the transaction stalls (to protect the register file and to avoid
executing bad instructions), and does not complete until it receives an interrupt signalled by a
peripheral block through the assertion of int
or cint, for example. This interrupt signalling typically
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